1. Field of the Invention
This invention is in the field of synchronous central processor units of large-scale, high-performance, general-purpose, digital data processing systems. More particularly, this invention relates to a method and apparatus for initiating the execution of instructions in a series of stages, each stage of which requires a single clock period so that, under optimum circumstances, an instruction is executed or is ready for execution by one of a plurality of execution units at a rate of one per clock period.
2. Description of the Prior Art
To increase the performance of central processing units (CPU's) of data processing systems of which they are a part, many modifications and improvements have been incorporated into such CPU's. One such modification is the use of a high-speed cache unit located in the CPU to minimize the time required to fetch operands and instructions. To further increase the performance of CPU's, they are synchronized. i.e., a clock produces a clock pulses which control each step, or stage, of the operation of the CPU. Synchronization permits paralleling, overlapping, or pipelining the execution of instructions by dividing the process of executing each instruction into a number of sequential steps, with each instruction going through the same sequence of steps one after another.
In a CPU having several execution units, with each execution unit being capable of executing a subset of the instruction repertoire of the CPU, it is desirable that the process of initiating the execution of instructions, including the fetching of the operand, or target word, of each instruction, be conducted in a series of steps or stages, each requiring one clock period to complete and through whch each instruction progresses so that, at the completion of the last stage, an instruction and its operand or target word is available and ready for execution or is executed by the appropriate execution unit, including those instructions which require only a single clock period to execute.